The trench Schottky rectifiers have been added externally in parallel to a semiconductor power device, e.g., a power trench MOSFET device for higher efficiency DC/DC applications. In parallel with the parasitic PN body diode, the trench Schottky rectifier acts as clamping diode to prevent the body diode from turning on. Therefore, many kinds of configuration have been proposed in prior arts to integrate the trench MOSFET and the trench Schottky rectifier on a single substrate.
FIG. 1A shows the side cross-section of an integration configuration of a prior art (U.S. Pat. No. 6,351,018) wherein both trench MOSFET and trench Schottky rectifier are sharing a common trench gate. As shown in FIG. 1A, The disclosed integration configuration is formed on an N doped substrate 102. A plurality of trenches are etched inside the substrate 102 and filled with doped poly within trenches to serve as trench gates 106 and 106′ over a layer of gate oxide 104. Between trench gates 106′, trench Schottky rectifier 110 is formed with a space width of W. Near the top surface of P well regions 108 in trench MOSFET, N+ source regions 112 are implanted adjacent to the sidewalls of trench gates. Body regions 114 heavily doped with P doping type are formed inside the P well regions 108. Metal layer 120 is connected to source regions 112, body regions 114 in trench MOSFET and is connected to anode of trench Schottky rectifiers via planar contacts 116 and 118, respectively.
Another integration configuration was proposed in U.S. Pat. No. 6,593,620 where trench MOSFET and trench Schottky rectifier have separated trench gates, as shown in FIG. 1B. The integration configuration comprising a DMOS transistor 220 and a trench Schottky rectifier 222 further includes an N+ substrate 200 onto which a lighter N doped epitaxial layer 202 is grown. A plurality of trench gates 210 are formed into the epitaxial layer 202 with gate oxide 206 padded on the filling-in material. The DMOS transistor 220 further comprises P body region 204 extending between trench gates 210 with N+ source regions 212 near its top surface adjacent to the sidewalls of trench gates. A metal layer 216 is connected to source regions 212, body regions 204 in DMOS transistor and is connected to anode of trench Schottky rectifier via planar contact. An insulating layer 235 is deposited on top of the trench gates 210 of the DMOS transistor 220 to isolate the metal layer 216 from the trench gates 210. On the rear side of wafer, metal layer 230 is deposited to act as a common drain contact for DMOS transistors and as a common cathode electrode for trench Schottky rectifiers.
Both structures mentioned above can achieve the integration of trench MOSFET and trench Schottky rectifier on a single substrate, but it's should be noticed that, planar contacts are employed in both trench MOSFET and trench Schottky rectifier to contact the source regions and the body regions with source metal, and to contact the anode with anode metal, respectively. Especially for trench MOSFET, the planar contact will limit device shrinkage because that, the planar contact occupies a large area, resulting in a high specific on-resistance in trench MOSFET.
Another constraint of the prior art is that, please refer to FIGS. 1A and 1B, metal step coverage of the prior arts will become poor if single metal is used to fill the planar contact when the planar contact dimension is shrunk.
Accordingly, it would be desirable to provide new and improved device configuration to avoid the high specific on-resistance caused by planar contact in trench MOSFET while having a better metal step coverage capability.